1. Field of the Invention
The present invention relates to a non-volatile ferroelectric memory, and more particularly, to a circuit for driving a split wordline (SWL) ferroelectric memory.
2. Background of the Related Art
A ferroelectric random access memory (FRAM) has a data processing speed as fast as a DRAM and conserves data even after the power is turned off. The FRAM includes capacitors similar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not lost even after eliminating an electric field applied thereto.
FIG. 1A illustrates a general hysteresis loop of a ferroelectric substance, and FIG. 1B illustrates a construction of a unit capacitor in a background art ferroelectric memory. As shown in the hysteresis loop in FIG. 1A, a polarization induced by an electric field does not vanish, but remains at a certain portion ("d" or "a" state) even after the electric field is cleared due to an existence of a spontaneous polarization. These "d" and "a" states may be matched to binary values of "1" and "0" for use as a memory cell. Referring to FIG. 1B, the state in which a positive voltage is applied to a node 1 is a "c" state in FIG. 1A, the state in which no voltage is applied thereafter to the node 1 is a "d" state. Opposite to this, if a negative voltage is applied to the node 1, the state moves from the "d" to an "f" state. If no voltage is applied to the node 1, thereafter the state moves to an "a" state. If a positive voltage is applied again, the states moves to the "c" state via the "b" state. At the end, even if there is no voltage applied on both ends of a capacitor, a data can be stored in stable states of "a" and "d". On the hysteresis loop, "c" and "d" states correspond to a binary logic value of "1", and "a" and "f" states correspond to a binary logic value "0".
In reading a data from the capacitor, the "d" state is destroyed to read the data stored in the capacitor. In a background art, a sense amplifier is used for reading a data using a voltage generated in a reference voltage generator and a voltage generated in a main cell array. In a ferroelectric reference cell, two modes of "1" polarity and "0" polarity are used for generating a reference voltage on a reference bitline. Accordingly, the sense amplifier compares a bitline voltage on a main cell and a reference bitline voltage on a reference cell, to read information in the main cell. By rewriting the read data within the same cycle, the destroyed data can be recovered.
A background art FRAM will be explained with reference to the attached drawings. There are FRAMs having a transistor and a capacitor (1T/1C) in a unit cell and FRAMs having two transistors and two capacitors (2T/2C) in a unit cell. FIG. 2 illustrates a background art 1T/1C FRAM cell array.
Referring to FIG. 2, the background art 1T/1C FRAM cell array is provided with a plurality of wordlines W/L arranged in one direction spaced at fixed or prescribed intervals, a plurality of platelines P/L arranged between wordlines in parallel thereto, and a plurality of bitlines B1, - - - , Bn arranged in a direction vertical to each of the wordlines W/L and the platelines P/L. Each of the transistors in a unit memory cell has a gate electrode connected to one of the wordlines W/L, a source electrode connected to an adjacent bitline B/L, and a drain electrode connected to a first electrode of the capacitor and a second electrode of the capacitor connected to an adjacent plateline P/L.
FIGS. 3A and 3B illustrate a circuit for driving the background art 1T/1C FRAM, FIG. 4A illustrates timings of signals for a writing operation of the background art 1T/1C FRAM cell, and FIG. 4B illustrates timings of signals provided for explaining a reading operation of the background art 1T/1C FRAM cell.
The circuit for driving the background art 1T/1C FRAM includes a reference voltage generator 1 for generating a reference voltage, and a reference voltage stabilizer 2 having a plurality of transistors Q1.about.Q4 and a capacitor C1 for stabilizing a reference voltage on two adjacent bitlines B1 and B2 because the reference voltage from the reference voltage generator 1 cannot be provided to a sense amplifier directly. A first reference voltage storage circuit 3 having a plurality of transistors Q6.about.Q7 and capacitors C2.about.C3 for storing of a logic value "1" and a logic value "0" in adjacent bit lines, and a first equalizer 4 having a transistor Q5 for equalizing adjacent two bitlines. A first main cell array 5 having a plurality of transistors Q8, Q9, - - - , and ferroelectric capacitors C5, C6, - - - , connected to wordlines W/L and platelines P/L for storing data, and a first sense amplifier 6 having a plurality of transistors Q10.about.Q15 and P-sense amplifiers PSA senses a data in a cell selected by the wordline from the plurality of cells in the main cell array 5.
A second main cell array 7 having a plurality of transistors Q26, Q27, - - - , and capacitors C7, C8, - - - , connected to wordlines and platelines different from one another to store data, and a second reference voltage storage circuit 8 having a plurality of transistors Q28.about.Q29 and capacitors C9.about.C10 to store a logic value "1" and a logic value "0" in adjacent bit lines. A second sense amplifier 9 having a plurality of transistors Q16.about.Q25 and N-sense amplifiers NSA to sense a data in the second main cell array 7.
Referring to FIG. 4A of the writing mode, upon enabling a CSBpad signal, a chip enable signal, from "high" to "low" externally, a writing mode enable signal WEBpad also transits from "high" to "low", to start the writing mode. An address decoding is started, to transit from "low" to "high" on a selected line to select a cell. During the wordline is held at "high", a corresponding plateline P/L is applied of an interval of "high" signal and an interval of "low" signal in a sequence. For writing a logic "1" or "0" on the selected cell, "high" or "low" signal is applied to a corresponding bitline synchronous to the writing enable signal. Namely, if "high" signal is applied to the bitline for writing a logic value "1", the logic value "1" is written on the ferroelectric capacitor within an interval of the wordline being "high" at a time when the plateline signal is "low", and for writing logic value "0", if a "low" signal is applied to the bitline, a logic value "0" is written in the ferroelectric capacitor when the plateline signal is "high". Thus, either a logic value "1" or a logic value "0" is written.
Referring to FIG. 4B of a reading mode, when CSBpad signal, a chip enable signal, is enabled from "high" to "low" externally, before selection of a corresponding wordline, all bitlines are equalized to "low" by an equalizer signal. That is, in FIG. 3, when "high" signal is applied to the equalizer 4 and "high" signal is applied to transistors Q19 and Q20, which grounds the bitlines through the transistors Q19 and Q20, the bitlines are equalized to "low". Transistors Q5, Q19 and Q20 are turned off, disabling corresponding bitlines, and address is decoded for transiting a corresponding wordline from "low" to "high", to select a corresponding cell. Then, a "high" signal is applied to a plateline of the selected cell, to cancel data corresponding to a logic value "1" stored in an FRAM. If the FRAM is in storage of a logic value "0", a data corresponding to it will not be canceled. A cell with a canceled data and a cell with a data not canceled provide signals different from each other according to the aforementioned hysteresis loop principle.
Data provided through bitline is sensed by the sense amplifier of a logic value "1" or "0". That is, referring to FIG. 1, since the case of a canceled data is a case when a state is changed from "d" to "f", and the case of a data not canceled is a case when a state is changed from "a" to "f", if the sense amplifier is enabled after a certain time, in the case of the canceled data, the data is amplified to provide a logic value "1", and, in the case of the data not canceled, the data is amplified to provide a logic value "0". After the sense amplifier amplifies and provides a signal, since the cell should be recovered of an original data, during "high" is applied to a corresponding line, the plateline is disabled from "high" to "low".
However, in the background art 1T/1C FRAM, in which the reference cell is operative more than the main memory cell, the reference cell degrades rapidly, providing an unstable reference voltage. Further, the regulation of the reference voltage by using a voltage regulating circuit is also not stable due to influences from an external power characteristic and noise. One solution in place of the background art 1T/1C FRAM having the aforementioned problems, is the 2T/2C FRAM.
Referring to FIG. 5, the array of the background art ferroelectric memory cells, each unit memory cell having two transistors and two capacitors (2T/2C) is provided with a plurality of wordlines W/L arranged in one direction and spaced at fixed intervals. A plurality of platelines P/L are arranged parallel to the wordlines and between each of the wordlines W/L. A plurality of bitlines B.sub.-- n, B.sub.-- n+1 and bitbarlines BB.sub.-- n, BB.sub.-- n+1 are arranged alternatively and in a direction vertical to the wordlines W/L and the platelines P/L.
The gate electrodes of the two transistors T1 and T2 in a unit memory cell 21 are connected to an adjacent wordline W/L in common, and the source electrodes of the transistors T1 and T2 are connected to an adjacent bitline B.sub.-- n and bitbarline BB.sub.-- n, respectively. The drain electrodes of the transistors T1 and T2 are connected to the first electrodes of two capacitors, respectively, while the second electrodes of the capacitors are connected in common to an adjacent plateline P/L.
The array of the background art 2T/2C FRAM cells writes and reads a logic value "1" or "0" as follows. Referring to FIG. 6A, in a writing mode, when a chip enable signal CSBpad transits from a "high" to a "low" externally, the array is enabled, and simultaneously, a writing mode enable signal WEBpad also transits from a "high" to a "low" to provide "high" and, "low" or "low" and "high" signals to the bitline and the bitbarline according to a logic value intended to be written. An address is decoded to transit a wordline signal of a selected cell from a "low" to a "high" for selecting the cell.
During an interval in which the wordline is held at a "high", a "high" signal of a fixed interval and a "low" signal of fixed interval in succession are applied to a corresponding plateline P/L. For writing a binary logic value "1", a "high" signal is applied to a bitline B-n and a "low" signal is applied to a bitbarline BB-n. For writing a binary logic value "0", a "low" signal is applied to a bitline B-n and "high" signal is applied to a bitbarline BB-n. Thus, either a logic value "1" or a logic value "0" can be written into the capacitor C1 or C2.
Referring to FIG. 6B, when a chip enable signal CSBpad transits from a "high" to a "low" and a write mode enable signal WEBpad transits from a "low" to a "high", the write mode is deactivated and a read mode is enabled. Before selection of a required wordline, all bitlines are equalized to a "low" level by an equalization signal. After completion of the equalizing to the "low" level, an address is decoded to transit a signal on the required wordline from a "low" to a "high" for selecting a corresponding unit cell. A "high" signal is applied to a plateline of the selected cell to cancel a data on the bitline or the bitbarline.
In other words, if a logic value "1" is written, a data in a capacitor connected to the bitline will be destroyed, and if a logic value "0" is written, a data in a capacitor connected to the bitbarline will be destroyed. Thus, depending on the data destroyed on the bitline or on the bitbarline, a value different from each other is provided according to the hysteresis loop characteristics. When the data provided through either the bitline or the bitbarline is sensed by the sense amplifier, the data value will be either logic "1" or logic "0". After the sense amplifier amplifies and provides the data, since the cell should have the data recovered, during the required wordline is applied of "high", the plateline is disabled from a "high" to a "low".
In spite of its merit that a stored data is kept when the power is off, the conventional FRAM has a complex layout because of their separated plate lines, and therefore, the manufacturing process is also complicated. Further, the speed of the conventional FRAM decreases because the data input and output operations are done by the separated plate lines, and a control signal is applied to the plate lines for the data read and write operations.
The integration in the conventional ferroelectric memory cell also cannot be improved without developing a new electric material or a new barrier material.
Another important factor causing a serious problem in the integration is that the area of a FRAM is larger than that of DRAM having the same capacity since a capacitor cannot be formed on a silicon substrate or on a surface of polysilicon because of lack of technique forming a ferroelectric layer on a surface of silicon. Moreover, it is difficult to exactly control the operation of the memory device since the wordline and the plate line are separately controlled, and therefore, there is a difference between control signals according to the transmission path.
Further, particularly in the background art 1T/1C FRAM, since one reference cell of a ferroelectric substance of which ferroelectric property is not fully assured is provided for a few hundreds of main memories for use in reading operation, requiring much more operation of the reference cell, the reference cell is involved in a rapid degradation of the ferroelectric property, causing instability of the reference voltage.